1. Field of the Disclosure
The present disclosure relates generally to electronic devices and more particularly to memory devices.
2. Description of the Related Art
A typical memory module includes a memory array having a plurality of select interconnects that are used to access a specific portion of the memory array during an access cycle. The select interconnects typically include a plurality of spatial select interconnects. The term “spatial select interconnect” as used herein refers to select interconnects of a memory array associated with a common spatial orientation. Examples of spatial select interconnects includes, wordlines, column select lines, and block select lines. A memory address that identifies a portion of memory to be accessed is received at a decoder of the memory module and decoded during a memory access cycle to provide a spatial select pattern to the spatial select interconnects. A memory access error occurs when a spatial select pattern results in multiple spatial select interconnects being enabled during the same memory cycle. Such access errors can be the result of manufacturing errors, a hard error, or spurious one-time events, a soft error.
In order to detect access errors, and thereby increase the reliability of a memory module, it has been proposed that the actual spatial select pattern at a spatial select interconnect be encoded to determine an encoded address that should match the address received at the memory module. When the encoded address matches the actual address the access of the current access cycle is verified. However, when the encoded address does not match the actual address, the access of the current access cycle is not validated.